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FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory and PL AXI4-Stream FIFO

In this episode, we're building a complete Zynq SoC FPGA application demonstrating direct memory access (DMA) in both directions between the processing system's DDR memory and another block of memory with an AXI4-stream interface residing in the programmable logic fabric.
The application is validated on the pynq-z1 board.

The DMA engine is configured by the C application through the AXI4-Lite interface to initiate DMA-read and DMA-write operations. In DMA-read operation, a block of 16 32-bit incrementing numbers is transferred from the DDR to the AXI4-Stream FIFO data buffer. That block of data from the AXI4-Stream FIFO is then moved back to the DDR at a different memory location through a DMA-write operation. The received data is then read and verified to validate the complete DMA application works as intended.

#fpga #zynq #vivado #vitis #embedded #verilog #xilinx

Related Zynq SoC FPGA episodes:

FPGA 29 - Zynq SoC FPGA XADC application to measure on-chip power supply voltages and die temperature
https://youtu.be/n-Ntei5nsRM

FPGA 27 - Zynq SoC FPGA PL interrupts PS to trigger software execution
https://youtu.be/luD2y81pD8s

FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)
https://youtu.be/p0nIpCgMUg8

FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)
https://youtu.be/kjPQw_iNN-8

FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LEDs
https://youtu.be/_sW6WGgaa10

Recommended prerequisites:

FPGA 1 - Set up AMD Xilinx Vivado/Vitis (free version)
https://youtu.be/yMSXtVs0pxE

FPGA 3 - First Verilog Vivado project for beginners
https://youtu.be/6usXS4eBQJ8

FPGA 4 - First VHDL Vivado project for beginners
https://youtu.be/voaeHwcglg8

FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
https://youtu.be/CiMUVkX-cOo

Видео FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory and PL AXI4-Stream FIFO канала FPGA Revolution
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9 августа 2023 г. 23:07:54
00:06:42
FPGA Revolution
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