FPGA 32 - Transition-minimized differential signaling (TMDS) 1280x720p @60fps RGB video over HDMI

We're building a complete FPGA RTL design to generate transition-minimized differential signaling (TMDS) RGB video over HDMI with a resolution of 1280x720p at 60 frames per second.

In addition to using two IP blocks for clock synthesis and video timing generation, we'll code up three RTL modules. One to handle TMDS 8b10b data encoding. One to handle the serialization of encoded 10-bit TMDS data onto the channels over HDMI interface. The third top level module glues everything together enabling the transmission of red, green and blue video frames onto the HDMI interface.

At the end we'll program the FPGA on the pynq-z1 board and verify the result on a receiving HDMI monitor.

#fpga #vivado #verilog #xilinx #hdmi #rgb #pixel #video #fps

Zynq SoC FPGA episodes:

FPGA 31 - Zynq SoC FPGA Data acquisition to SD card (Acquisition / DMA and record to SD card)
https://youtu.be/vVLn73TkpBs

FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory space and PL AXI4-Stream FIFO
https://youtu.be/tQpt2N7__NQ

FPGA 29 - Zynq SoC FPGA XADC application to measure on-chip power supply voltages and die temperature
https://youtu.be/n-Ntei5nsRM

FPGA 27 - Zynq SoC FPGA PL interrupts PS to trigger software execution
https://youtu.be/luD2y81pD8s

FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)
https://youtu.be/p0nIpCgMUg8

FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)
https://youtu.be/kjPQw_iNN-8

FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LEDs
https://youtu.be/_sW6WGgaa10

Recommended prerequisites:

FPGA 1 - Set up AMD Xilinx Vivado/Vitis (free version)
https://youtu.be/yMSXtVs0pxE

FPGA 3 - First Verilog Vivado project for beginners
https://youtu.be/6usXS4eBQJ8

FPGA 4 - First VHDL Vivado project for beginners
https://youtu.be/voaeHwcglg8

FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
https://youtu.be/CiMUVkX-cOo

Видео FPGA 32 - Transition-minimized differential signaling (TMDS) 1280x720p @60fps RGB video over HDMI канала FPGA Revolution