RISC-V Day Tokyo 2025 Spring: CHERI - How it works by Takaaki Akashi, Japan, Codasip GmbH

RISC-V Day Tokyo 2025 Spring: CHERI - How it works by Takaaki Akashi, Counrtry Manager-Japan, Codasip GmbH (Germany)

The presentation demonstrates how CHERI works in practice by using the Codasip X730 RISC-V Core in an FPGA Evaluation Kit as a platform for live, real-world demonstration. The X730 is notable because it is the first commercially-licensable RISC-V core that implements the CHERI extensions (Capability Hardware Enhanced RISC Instructions) directly in the microarchitecture, combining security and memory-safety features into a mainstream processor.

In the demonstration, the FPGA evaluation kit serves as a complete system platform: it includes the X730 core, memory subsystems and capability-tag hardware support, peripheral IP, secure boot and debug hardware, and a software stack including CHERI-enabled Linux and tools.

The storyboard format implies that the talk will walk attendees step-by-step—starting from the hardware architecture modifications required to support CHERI (such as extended register files, capability tag memory support, modifications to load/store pipelines) and proceeding through system-level integration, software toolchain support, demonstration of applications running with CHERI protections enabled, and finally discussion of measured performance and security benefits on the evaluation kit. For example, the X730 registers and some CSRs are extended to 129 bits to accommodate capabilities, and the memory system is modified to atomically handle capability tags while retaining standard interfaces.
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During the demonstration portion, the presenter may show how pointer misuse attacks (such as buffer overflow or out-of-bounds access) are prevented on the hardware by CHERI capabilities, illustrate how legacy binaries and recompiled CHERI-aware binaries behave differently on the X730, and discuss the nominal performance and area overhead of the CHERI implementation (early results indicate that performance remains comparable to the baseline processor with only a small area increase).

Finally, the talk will outline how engineers and system designers can use this FPGA evaluation kit to develop CHERI-aware software and hardware, experiment with CHERI’s memory safety features, evaluate the practicality of deploying CHERI-enabled RISC-V systems in embedded, automotive, data-center or IoT contexts, and prepare for mainstream adoption. The platform is significant because it marks the shift of CHERI from academic research to commercial availability.

Видео RISC-V Day Tokyo 2025 Spring: CHERI - How it works by Takaaki Akashi, Japan, Codasip GmbH канала Shumpei Kawasaki