RISC-V Day Tokyo 2025 Spring: Interface of the Pulp project for RISC-V core by Hideharu Amano etal.

RISC-V Day Tokyo 2025 Spring: Interface of the Pulp project for RISC-V core by Hideharu Amano, Takuya Kojima (University of Tokyo) and Morihiro Kuga (Kumamoto University)

SLMLET is a compact, low-power System-on-a-Chip (SoC) designed specifically for edge computing environments, where power efficiency and flexibility are critical. The chip integrates a RISC-V processor core together with small, area-efficient embedded FPGAs known as Scalable Logic Modules (SLM). These SLM blocks function as reconfigurable hardware units, allowing developers to implement custom accelerators directly on the chip without the need for an external FPGA.

The presented work showcases an actual fabricated SLMLET chip along with a complete hardware/software co-design flow that enables engineers to partition workloads between the RISC-V processor and the SLM hardware blocks. Performance measurements show that the RISC-V core can run at up to 300 MHz, while designs implemented on the SLM blocks operate at up to 100 MHz—fast enough for a wide range of embedded and IoT applications.

A key result is the significant energy savings achieved through hardware offloading. By moving computationally heavy tasks—such as signal processing or repeated arithmetic operations—from the software running on the RISC-V core to specialized hardware circuits implemented in the SLM blocks, the system reduces energy consumption by up to 77% compared with running the same tasks on the CPU or even on other commercial microcontrollers. This demonstrates that combining RISC-V with lightweight, embedded FPGA logic provides a powerful platform for efficient edge computing, offering both programmability and hardware-level acceleration in a single SoC.

Видео RISC-V Day Tokyo 2025 Spring: Interface of the Pulp project for RISC-V core by Hideharu Amano etal. канала Shumpei Kawasaki