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Architecture Exploration of System-on-chip using VisualSim ARM and RISC-V Hybrid Library
Architecture exploration provides 80% of system optimization and 100% of power/performance trade-offs. The lack of accurate, feature-rich, and easy-to-use modeling components has prevented companies from taking advantage of this phase of product design. During this Webinar, we will utilize VisualSim hybrid processor family to construct a multi cluster-multi core NoC-based SoC model, simulate with software traces, generate reports on latency, throughput, cache hot-ratio, memory bandwidth and power consumption, and optimize the architecture to meet the requirements. The SoC model will be assembled using standard library components for ARM A53, ARM A65AE and SiFive RISC-V u74, Arteris FlexNoC, ARM CMN600, TileLink, AMBA AXI, DDR4 and LPDDR5
Key Takeaways:
1. Learn to use a system model to architect RISC-V cores, and detect latency, throughput and buffer limits.
2. Partitioning workload across multiple clusters and integrate the AI accelerators into the flow.
3. Measure the impact of power management algorithms on the instant and average power consumption of the system.
4. Use architecture models for software performance tuning,
Who should attend: Program manager, Architects, Performance Engineer, Firmware and embedded software developers.
SPEAKER: Deepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of over 250 SoC and processors. Mr. Shankar started Mirabilis Design because of a vacuum in the systems engineering and modeling space with the focus shifting to network design and early software development. Deepak has published over 50 articles and presented at over 30 conferences in EDA, semiconductors and embedded computing. Mr. Shankar has an MBA from UC Berkeley, MS in from Clemson University and BS from Coimbatore Institute of Technology, both in Electronics and Communication.
Видео Architecture Exploration of System-on-chip using VisualSim ARM and RISC-V Hybrid Library канала VisualSimSolutions
Key Takeaways:
1. Learn to use a system model to architect RISC-V cores, and detect latency, throughput and buffer limits.
2. Partitioning workload across multiple clusters and integrate the AI accelerators into the flow.
3. Measure the impact of power management algorithms on the instant and average power consumption of the system.
4. Use architecture models for software performance tuning,
Who should attend: Program manager, Architects, Performance Engineer, Firmware and embedded software developers.
SPEAKER: Deepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of over 250 SoC and processors. Mr. Shankar started Mirabilis Design because of a vacuum in the systems engineering and modeling space with the focus shifting to network design and early software development. Deepak has published over 50 articles and presented at over 30 conferences in EDA, semiconductors and embedded computing. Mr. Shankar has an MBA from UC Berkeley, MS in from Clemson University and BS from Coimbatore Institute of Technology, both in Electronics and Communication.
Видео Architecture Exploration of System-on-chip using VisualSim ARM and RISC-V Hybrid Library канала VisualSimSolutions
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5 августа 2021 г. 9:07:11
00:39:25
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