Designing System-on-chip with NoC (Network-on-Chip), HBM2.0 (High Bandwidth Memory), DDR5, ARM Z1

This Webinar covers the architecture exploration of System-on-Chip. The focus is on extremely high-performance processors used for real-time packet processing, high-performance computing and large defense systems. The Webinar goes over the methodology, how to construct models, analyze and make decisions. The IP used or discussed include
NoC- Corelink and CMN600
Processors: RISC-V, ARM A77 and ARM A53
Memory: L3 Cache, HBM2.0 and DDR5
DMA
Traffic Generators
Reports for power consumption, latency, throughput and quality of service.

Видео Designing System-on-chip with NoC (Network-on-Chip), HBM2.0 (High Bandwidth Memory), DDR5, ARM Z1 канала VisualSimSolutions