Accuracy-Performance-Resources Trade-Offs in RISC-V Microarchi. for G.P. - Paul Allaire

Presentation of the 2026 Computing Frontiers publication "Accuracy-Performance-Resources Trade-Offs in RISC-V Microarchitectures for Genetic Programming" by Paul Allaire (IETR Vaader)

Abstract

Among machine learning techniques, Genetic Programming (GP) flexibly adapts algorithm topology and complexity to the target problem. This adaptability makes GP models computationally efficient at inference, requiring fewer resources than many alternatives. This property aligns well with resource-constrained embedded systems with diverse performance and energy requirements.
Efficiently deploying GP models on low-power systems is challenging, requiring adequation between model parameters and hardware. However, current state of the art lacks an automated approach for identifying the optimal pairing between hardware platforms and GP model configurations under accuracy, performance, and resource constraints. Consequently, system designers are either relying on empirical, time-consuming trial-and-error methods, or forgo hardware specialization altogether.
This work introduces a comprehensive Hardware/Software co-exploration methodology for evaluating GP models on resource-constrained embedded systems. The proposed framework explores exhaustively design parameters to identify optimal trade-offs among accuracy, performance, and resource usage.
We demonstrate it on 18 RISC-V microarchitectures (𝜇archs) implementing 15 Tangled Program Graphs (TPGs). We reveal latency variations of up to two orders of magnitude, accuracy differences of up to 5%, and normalized resource usage variations of up to 57% thus providing system designers with Pareto fronts enabling data-driven decisions.

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