Suricata IDS + FPGA SmartNIC Demo on 400Gbps | Flow-Based Acceleration with DYNANIC

This video demonstrates how *Suricata can offload selected traffic flows to an FPGA-based SmartNIC using the DYNANIC* packet-processing pipeline.

Suricata identifies relevant traffic (e.g., based on 5-tuple) and instructs the FPGA to handle it directly in hardware - reducing CPU load and improving overall system efficiency.

A key aspect of this approach is HW platform independence: the solution is built on a standard DPDK-based stack provided by DYNANIC, allowing seamless integration into existing software environments without hardware vendor lock-in or application changes.

🔍 Demo highlights:

* Suricata ↔ FPGA interaction via DPDK
* Platform-independent packet processing stack
* Flow-based traffic handling
* Inline processing on SmartNIC

⚡ By offloading packet processing from CPU to FPGA, this approach helps reduce infrastructure requirements and lower the total cost of IDS deployments, while maintaining the flexibility of software-based detection.
📄 Learn more in our whitepaper (including future development directions):
👉 https://dyna-nic.com/wp-content/uploads/2025/02/Acceleration-of-Suricata-IDS.pdf

🌐 https://dyna-nic.com
#Suricata #FPGA #SmartNIC #Cybersecurity #IDS #PacketProcessing #DPDK #HardwareAcceleration #NetworkSecurity #DYNANIC

Видео Suricata IDS + FPGA SmartNIC Demo on 400Gbps | Flow-Based Acceleration with DYNANIC канала DYNANIC