FPGA SoC Series #3: AXI4-Lite Read IP Design

In this video, we design a custom AXI4-Lite read slave IP in Verilog and explain how a MicroBlaze processor can use an AXI4-Lite read command to request data from custom hardware. The lesson covers how an AXI4-Lite read transaction works, the two phases of the read command, and the key signals used during the read address phase and read data phase. Then, we use those ideas to build a Verilog ROM IP block that stores predefined values and returns them when the processor reads from the correct addresses. This is Lesson #3 in the FPGA SoC series and completes the basic AXI4-Lite read/write foundation needed to build processor-controlled FPGA systems.

💻 Digital Editions (Instant Access + Discount): https://truesightlabs333.com/

📚 Physical Editions (Amazon):
📗 Introduction to Verilog: https://www.amazon.com/dp/B0D92325VC
📘 Verilog-Based Robotics & Signal Processing: https://www.amazon.com/dp/B0F7QVT2T8

📺 Full Playlist: https://www.youtube.com/playlist?list=PLfPwG72dAOx6gkqrrZVdr63EaizecO0Cg

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🎓 Who This Course Is For
• Electrical & Computer Engineering students
• FPGA engineers seeking real project experience
• Intermediate Verilog users ready for expert-level skills
• Anyone preparing for a career in FPGA/ASIC hardware design

⏱️ Video Chapters
0:00 Intro
1:10 AXI4-Lite Explained
3:45 Problem Description
4:32 Verilog Code
8:28 Block Diagram
13:25 Vitis
15:50 Homework
18:30 Vitis
22:08 Promotion

#FPGA #Verilog #Artix7 #ControlSystems #ADC #SignalProcessing #DigitalDesign #Robotics #digitaldesign

Видео FPGA SoC Series #3: AXI4-Lite Read IP Design канала Emilio Martinez III