Structural Architecture in VHDL - ModelSim

This video (non-audio) demonstrates describing our hardware through VHDL, for making a Half Adder.

For this, custom entities for XOR and AND are created, and then wired using Structural Modelling.

Structural Modelling is simply the wiring of many sub-entities INSIDE a main entity in order to obtain desired outputs. Very similar to how we make logic diagrams on paper and expect them to work.

Видео Structural Architecture in VHDL - ModelSim канала Aryan Aich