Standard Cell Marathon : Key Concepts, Classifications, Design and Characterization

Chapters :
00:00:00 Beginning
00:02:58 IP/SIP
00:03:40 Building Block
00:05:38 IP & Core
00:08:45 Journey
00:10:33 Why IP ?
00:13:29 End-Use
00:16:30 By Genre
00:18:05 By Size
00:19:43 By Distribution
00:21:29 By Circuit Nature
00:22:03 Soft and Hard IP
00:23:47 IP Example
00:26:03 Summary
00:28:07 Std Cell Library
00:29:00 Building Block
00:31:02 Intro
00:33:35 Classification
00:35:08 What's Inside
00:37:17 VLSI Design Flow
00:37:42 FE Views
00:39:10 BE Views
00:40:01 Variations
00:43:30 Summary
00:45:21 IP Views
00:46:08 View Means ?
00:47:59 RTL Views
00:49:55 Timing Views
00:51:07 Transistor Level Views
00:52:14 Layout Views
00:53:29 Phy-Ver Views
00:54:39 PEX Views
00:55:29 Macro Views
00:56:02 Summary
00:58:17 What is PDK-DK
00:59:19 Subdivisions
01:00:35 Init-Files
01:01:58 Technology Data
01:03:21 Phy Ver Decks
01:04:40 Std Cell Library
01:07:15 Memories
01:07:50 High-Speed Interfaces
01:08:34 Analog Blocks
01:09:22 Free-PDK Tour & Download
01:23:03 OASIS File
01:24:27 Intro
01:28:44 OASIS is Better
01:34:21 GDS Vs OASIS
01:37:59 Choice of present ?
01:39:54 Check-points
01:41:58 Open Access?
01:43:21 OA and OASIS
01:46:19 Conclusion
01:48:28 Standard Cell Char
01:49:26 Building Block
01:50:30 Std Cell Design Flow
01:53:26 CMOS Layout
01:55:08 Types of Cells
01:56:11 VT Variation
01:57:18 Track Variation
01:58:25 Drive Strength Variation
01:59:17 FE View Gen
02:00:05 BE View Gen
02:01:04 How Lib File Created ?
02:01:52 Characterization
02:03:57 Cell .lib Liberty
02:04:57 Summary
02:06:01 Lib File
02:06:45 How Lib Created ?
02:08:06 Introduction
02:11:11 Internal Format
02:12:11 Name Tokens
02:15:36 Header Section
02:17:35 LUT Section
02:19:20 Standard Cell Section
02:21:47 FF & Latch
02:22:58 Scan Chain
02:25:00 Header Section Example
02:29:15 Cell Begin & End Example
02:32:06 Cell Output-RiseDelay/LUT Example
02:33:51 Cell Output-Fall-Delay/LUT Example
02:35:09 Cell Output-RiseSlew/LUT Example
02:36:18 Cell Output-FallSlew/LUT Example
02:36:53 Basic Lvl Shifter Cell
02:37:33 Intro
02:39:45 Operation
02:42:09 Level Shifter Cells
02:44:28 Positioning Lvl Shftr Cells
02:47:08 Variants
02:48:33 Summary
02:50:04 Advanced Lvl Shifter Cell
02:50:57 Philosophy
02:52:33 Clock Domain Crossings
02:53:41 Voltage Domain Crossings
02:54:56 Cross Coupled Level Shifter
02:56:07 Boot Strap Level Shifter
02:57:09 DCVS Basic Level Shifter
02:58:53 DCVS Advanced Level Shifter
03:00:29 Summary
03:01:18 Retention Cell
03:02:11 Power Management
03:03:48 Retention Concept
03:06:11 Retention Flops
03:07:12 PSO and SRPG
03:08:19 Simulation & Verification Stage
03:09:43 Physical Design Stage
03:11:08 Categories
03:11:30 Balloon Type Retention Cell
03:12:28 Master-Slave Retention Cell
03:13:45 Summary
03:14:20 Isolation Cell
03:14:53 Various Power Management
03:16:00 Problem Scenario
03:18:28 Isolation Cell To The Rescue
03:20:25 Method and Isolation Cells
03:22:09 Detection Missing Isolators
03:23:18 Example
03:24:52 Drawbacks & Improvements
03:26:13 Summary
03:27:06 Decap Cell
03:28:11 Introduction
03:29:55 Why decoupling ?
03:32:44 Intrinsic and Extrinsic DECAPs
03:34:22 Positioning of DECAPs
03:35:30 ON CHIP DECAP
03:37:09 DECAPs & PD
03:38:51 FPGA & DECAPs
03:40:29 DECAP using NMOS
03:43:10 Filler Cell
03:44:07 Standard Cell Layout
03:47:35 Filler Cell
03:52:40 Design Automation
03:56:06 Physical Design Aspect
03:58:46 PD (DRC) Aspect
04:01:37 MBFF Cell
04:03:14 Introduction
04:05:22 Single Bit FF
04:05:56 2-Bit-MBFF
04:07:45 4-Bit-MBFF
04:09:27 Criterion of Implementation
04:12:05 MBFF in Implementation
04:15:44 VLSI Design Flow
04:18:24 MBFF in FE Flow
04:19:41 MBFF in BE Flow
04:21:43 Why PD Needed
04:22:25 Visualize PD
04:24:38 What is PD ?
04:28:06 PD is Must ?
04:30:08 PD in Analog Vs ASIC/SOC
04:33:20 PD FEOL
04:35:31 PD BEOL
04:37:08 FEOL-BEOL-MEOL
04:38:11 CMOS Process
04:39:05 Categorization
04:40:05 Chip Cross-Section
04:41:13 Front-End-of-Line (FEOL)
04:42:10 Middle End Of Line (MEOL)
04:42:43 Back-End-Of-Line (BEOL)
04:43:30 CMOS Layout
04:45:14 FEOL/BEOL in PD
04:48:03 Summary
04:48:52 Process Corners
04:49:55 CMOS Layout
04:51:19 PMOS Vs NMOS
04:53:58 Process Variation
04:55:17 Process (FEOL) Corners
04:57:03 Process Corners : Graphical
04:58:58 FEOL and BEOL Corners
04:59:56 FEOL Corner Names
05:00:43 Nomenclature
05:01:52 FEOL Corners Variation
05:04:19 FEOL+BEOL Combined
05:05:35 Summary
05:06:33 RC (BEOL) Corners
05:07:29 RC Extraction
05:10:19 Parasitics Visualization
05:11:28 Net R&C Overview
05:13:43 RC Corners
05:16:24 Name Alias
05:18:11 Tech Node Vs RC Corners
05:19:34 Corner Terminologies
05:21:13 PVT+RC Combined
05:23:25 Permutation & Combination
05:24:32 Improved Timing Sign-Off
05:25:36 Summary
05:26:28 What is PPA
05:27:38 Introduction
05:31:02 Power Optimization
05:35:52 Performance Optimization
05:41:22 Area Optimization

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