Gate Level Simulation (GLS) | Post-Synthesis Verification | Yosys Synthesis | Design verification

🚀 In this video, we will learn Gate Level Simulation using the Yosys tool step by step. We will understand how RTL is converted into a gate-level netlist and how to simulate that generated design to verify its functionality.

Topics covered in this video:
• Introduction to Gate Level Simulation
• Why Gate Level Simulation is important
• Yosys synthesis flow
• RTL to gate-level netlist generation
• Simulating the synthesized netlist
• Understanding waveforms and outputs
• Basic Verilog example with Yosys

This video is useful for students and beginners in VLSI, Digital Design, RTL Design, and Verification.

Formal Verification Video:
https://youtu.be/73w0LtlLIRk?si=1kEivQR5tAshF8lO

Tools used:
• Yosys
• QuestaSim

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#Yosys #GateLevelSimulation #Verilog #VLSI #Synthesis #physicalDesign #DigitalDesign #RTLDesign #Verification #Semiconductor

Видео Gate Level Simulation (GLS) | Post-Synthesis Verification | Yosys Synthesis | Design verification канала Awaiz - VLSI