Huawei’s "LogicFolding" Breakthrough: A 1.4nm Workaround for U.S. Chip Sanctions | Made with Ozor

Huawei semiconductor chief He Tingbo has unveiled the "Tau Scaling Law," a revolutionary roadmap centered on "LogicFolding" technology to sustain chip performance as traditional Moore's Law faces physical limits. This 3D stacking methodology vertically integrates digital, analog, and memory circuits, already demonstrating a 55% increase in transistor density and a 41% boost in energy efficiency on existing manufacturing nodes. By shifting the focus from "shrinking" to "folding," Huawei aims to produce 1.4-nanometer chips by 2031, narrowing the gap with industry leader TSMC without requiring restricted EUV lithography machines. The announcement triggered a 16% surge in shares for Chinese chipmakers like SMIC, as investors bet on Huawei’s ability to bypass U.S. sanctions through architectural innovation rather than just raw hardware. The first real-world test for this technology arrives later this year with the launch of next-generation Kirin mobile processors, which will be the first to implement early versions of LogicFolding. While mass-production challenges remain, Huawei envisions this shift driving a 100-fold increase in hardware integration by 2035, fundamentally altering the global race for AI and high-performance computing.

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Source: Bloomberg / Taipei Times

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