Mixed Electronic System Level Power/Performance using SystemC/TLM2.0 Modeling and PwClkARCH Library

Full title: Mixed Electronic System Level Power/Performance Estimation using SystemC/TLM2.0 Modeling and PwClkARCH Library

Presented at DVCon Europe 2020

The Hardware/Software (HW/SW) architectural exploration has become a key component of System on Chip (SoC) design modeling. The insufficient power and timing analysis capabilities at early stages of the design flow limits the optimized modeling. Pushed by the need to improve the methodology of early stages of design flow and inspired by the numerous studies on Electronic System Level (ESL) modeling, we introduce a novel ESL methodology that combines power and performance estimation in one unified framework. In this paper, we present our new approach applied and tested on an NXP proprietary switch matrix/interconnect system used in i.MX8 series of SoCs. Our model is based on SystemC-TLM2.0 and make use of PwClkARCH library for the power management. This framework allows us to develop a SoC transaction level model (TLM) written exclusively in C++/SystemC-TLM2.0 and to extract power consumption and performance metrics after the simulation. This modeling approach allows a strong separation between the functional SystemC/TLM model and its power intent description. Only a few pieces of code need to be added to performance model to hook power model to it. Moreover, it makes the code easier to debug and maintain.

Antonio Genov, Loic Leconte - NXP Semiconductors
François Verdier - University of Cote d’Azur, CNRS, LEAT

https://dvcon-europe.org
https://accellera.org

Видео Mixed Electronic System Level Power/Performance using SystemC/TLM2.0 Modeling and PwClkARCH Library канала Accellera